High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, AC/DC converters, etc.
There are a variety of forms of HVMOS devices. A symmetric HVMOS device may have a symmetric structure on the source side and drain side. High voltages can be applied on both drain and source sides. An asymmetric HVMOS device may have asymmetric structures on the source side and drain side. For example, only one of the source side and drain side, typically the drain side, is designed for sustaining high voltages.
FIG. 1 illustrates a conventional asymmetric HVNMOS device 2, which includes gate oxide 10, gate electrode 12 on gate oxide 10, drain (contact) region 4 in a high-voltage n-well (HVNW) region, and a source (contact) region 6 in a high-voltage p-well (HVPW) region. A shallow trench isolation (STI) region 8 spaces drain region 4 and gate electrode 12 apart so that a high drain-to-gate voltage can be applied. The HVNW region is formed on deep p-well (DPW) region 14.
HVNMOS device 2 suffers from drawbacks, however. FIG. 2 illustrates an I-V curve obtained from HVNMOS device 2, wherein the X-axis represents voltages Vd applied on drain region 4, and the Y-axis represents drive currents Id. It is noted that when operated in high-drain-current regions, for example, when high drain voltages Vd (about 50 volts or greater) and high gate voltages (about 5 volts or greater), are applied, the drive currents do not saturate with the increase in drain voltages, and an extra hump appears as in the dotted circle. This indicates an output resistance problem, which will cause the degradation in device reliability. Further, the existing SPICE models cannot simulate such a device behavior. Therefore, a solution for the above-discussed problem is needed.